In existing stacked semiconductor memory devices, memory cells are integrated in a three-dimensional manner. In such a stacked semiconductor memory device, referred to as a stacked body, electrode films and insulating films are alternately stacked on a semiconductor substrate, and semiconductor pillars penetrate through the stacked body. Memory cell transistors are formed at intersections between the electrode films and the semiconductor pillars. There is a need for ensuring reliability of memory cell transistors in such stacked semiconductor memory devices.